Table for Operating System – File Cache Alignment

Geeking Out on SSD Hardware Developments (Linux Magazine, February 9th, 2010)

Intel and Smaller Cells
“According to this link the theoretical lower limit on NAND cells appears to be around 20nm. One of the big reasons for this limitation is that as cells shrink in size they are, naturally, closer together. However, the voltage required to program a cell remains about the same (typically 12V). This means that the power density increases (amount of power in a given area) increasing the probability that the voltage will disturb the neighboring cells causing data corruption. Consequently, increasing the density of cells can be a dicey proposition, hence the lower limit.

Recently, IMFT (Intel-Micron Flash Technologies) LLC announced that it had begun sampling 2 bits per cell (MLC) NAND flash chips that have been manufactured using a 25nm process. This announcement is significant because of the increased density and how close the density is getting to the theoretical limit. Plus the fact that one of the best performing SSD drives is from Intel, one of the participating companies in the LLC, and we can see a fairly significant shift in technology.

IMFT is a joint project by Intel and Micro to develop new technologies around Flash storage (primarily NAND). The project started with production several years ago with a 72nm process. They then moved to a 50nm process in 2008 followed by a further reduction to a 34nm process in 2009. It is the 34nm process that current Intel SSDs utilize (Intel X25-M G2). The 34nm process produces a 4GB MLC NAND chip with a die size of 172 mm2.The new 25nm process is targeted for a first product which is an 8GB MLC NAND flash chip with a die size of 167 mm2. So going from 34nm to 25nm doubles the die density.

In addition to the doubling of die density the new chips will have some other changes. The current 34nm generation of chips have a page size of 4KB and 128 pages per block resulting in a block size of 512KB. The new chip will have a page size of 8KB and 256 pages per block. The means that the new block size is 8KB * 256 = 2,048KB (2MB). This change in block size can have a significant impact on performance.

Recall that a block is the smallest amount of storage that goes through an erase/write cycle when any single bit of the block is changed. For example, if any bit within the block is changed then the entire block has to first have the unchanged data copied from the block to cache and then the block is erased. Finally the updated information is merged with the cache data (unchanged data) and the entire block is written to the erased block. This process can take a great deal of time to complete and also uses a rewrite cycle for all of the cells in the block (remember that NAND cells have a limited number of rewrite cycles before they can no longer hold data).

The new 25nm chip will switch from 512KB blocks to 2MB blocks (2,048KB) increasing the amount of data that has to go through the read/erase/write cycle compared to the 34nm chips. To adjust to this change, Intel will have to make adjustments to the firmware to better handle the larger blocks. In addition, it is likely that Intel will have to at least double the cache size to accommodate the larger block sizes. It may have to increase the number of spare pages as well since a single bit change could cause a greater number of blocks to be tagged for updating. However, on the plus side, with larger pages, the controller can do much more optimization for writes including a much greater amount of write coalescing. But this too could increase the amount of cache needed.”

Chatwin’s Table

Conventional Allocation
4 KiB
Alignment
1 MB

Improved Allocation
64 KiB
Alignment
2 MB

OS – 32bit
File Level Cache

Page – 32 K
Size – 128 MB

Page – 64 K
Size – 256 MB

OS – 64bit
File Level Cache

Page – 64 K
Size – 256 MB

Page – 128 K
Size – 512 MB

OS – 32bit
Storage Level Cache

Page – 64 K
Size – 256 MB

Page – 128 K
Size – 512 MB

OS – 64bit
Storage Level Cache

Page – 128 K
Size – 512 MB

Page – 256 K stripe unit
Size – 1 GB

Cluster Unit Aligned
256 Kibit (32 KB)

Windows XP x32
(8*4)
System RAM: 2 GB

Physical Page Size:
32 Kibit (4 KB)
Logical Block Size:
128 KBytes

Sector Size – 512 bytes

Cluster Unit Aligned
512 Kibit (64 KB)

Windows XP x64
(8*8)
System RAM: 4 GB

Physical Page Size:
64 Kibit (8 KB)
Logical Block Size:
256 KBytes

Sector Size – 1024 bytes

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